Multi-component electronic package with planarized embedded-components substrate

ABSTRACT

An electronic multi-component package is assembled by placing multiple electronic components within multiple openings of a package substrate, then depositing and curing adhesive filler in gaps between the components and the inner peripheries of the openings. Circuit features, including conductive interconnects, are formed by thin-film photolithography over both front and back surfaces of the package substrate. Preformed conductive vias through the package substrate provide electrical connection between circuit features on opposite substrate surfaces. Additional electronic components may be attached to conductive lands on at least one side of the package. The circuit features also include contact pads for external package connections, such as in a ball-grid-array or equivalent structure.

TECHNICAL FIELD

The present invention relates to integrated circuit (IC) chip packagesand the mounting of one or more IC dice to a support substrate and/orframe together with associated circuit components and interconnects.

BACKGROUND ART

Multi-component electronic packages and system-in-package (SIP) packagesthat are employed in the electronics industry today all utilizesubstrates for device inter-connection and attachment. Typical organicsubstrate materials are epoxy-glass, polyimide, and fluoropolymerlaminates. Typical inorganic substrate materials are ceramics,low-temperature co-fire ceramics (LTCC) and silicon. The interconnectcircuitry and component attach features are fabricated onto thesubstrates prior to components assembly.

With the exception of a silicon substrate, which employs thin-film metaldeposition processes for the circuitry fabrication to yield linegeometries on the order of one micrometer, all of the other substratematerials yield line geometries that are 50 micrometers or larger. Asilicon substrate can only be used in single-sided applications and isoften fragile in the final package form. The larger line geometries ofthe other substrates necessitate a larger final package size. Theresultant longer interconnect lengths can also compromise packageperformance. Package designs with smaller package footprints and lowerprofiles, along with higher performance and yields, are ever beingsought in the electronics industry.

SUMMARY DISCLOSURE

The present invention is method of assembling a multi-componentelectronic package and the package so formed in which microelectronicintegrated circuit (IC) dice and/or discrete active/passive componentsare embedded into a “windowed” substrate carrier, planarized on both topand bottom surfaces. Electrically conductive interconnects anddielectric layers are deposited, or otherwise formed, on the top andbottom surfaces to electrically connect the embedded components.

In particular, a package substrate is provided, having defined front andback surfaces, with conductive vias through the package substrate.Multiple openings in the package substrate are sized to receiveelectronic components. After securing the package substrate on a vacuumsupport, multiple electronic components are placed within those openingsand secured in place by the vacuum support. Adhesive filler material isdeposited within a gap between the components and the inner peripheriesof the corresponding openings, and then the filler is cured so as topermanently secure the embedded electronic components within the packagesubstrate.

Circuit features are then formed in one or more layers over both frontand back surfaces of the package substrate, for example, by thin-filmphotolithography. Features on opposite surfaces are electricallyconnected to each other by means of the conductive vias through packagesubstrate. The circuit features include conductive interconnects thatare electrically connected to the multiple electronic componentsembedded within the substrate. Integrated passive features, such asinductors, can also be formed during the circuitry fabrication process.Additional electronic components can be attached to resulting structure,e.g., at metal lands. A land-grid array, ball-grid array or pin-gridarray can be formed on a back surface of the package substrate.

Package components are thus assembled onto the substrate to form anextremely compact, highly integrated, multi-component package orsystem-in-package (SIP) that provides an extremely small footprint andlow profile. The electrical performance of the package is improved dueto the ability to place the IC dice and other components in closeproximity. The thin-film conductive interconnects formed on theplanarized surfaces allow a much finer line width and spacing geometryin comparison with even the most advanced printed circuit boardtechnologies. It also allows precise, high Q, integrated passiveinductors to be formed in close proximity to the IC dice. With theinterconnect layers deposited directly above and below the IC dice, amore efficient use is made of the package's footprint area, resulting ina smaller package size. The standard die-attach, wire bond or flip-chipattach processes can be eliminated by using this embedded componentsmethod.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are respective top plan and side sectional views (thelatter taken through the line 1B-1B in FIG. 1A) of a wafer substrateserving as a starting point for assembly of a multi-component electronicpackage in accord with the present invention.

FIGS. 2A through 2H are respective side sectional views, analogous toFIG. 1B, at various stages in a process of assembling an electronicpackage in accord with the present invention.

DETAILED DESCRIPTION

With reference to FIGS. 1A and 1B, a wafer 10 forms a substrate 12 forone or more IC chip packages. When cut into sections, e.g., 14 ₁, 14 ₂,14 ₃, 14 ₄, each of those sections of the wafer 10 will define aseparate package. The substrate 12 is typically composed of a dielectricmaterial, such ceramics, glass, or plastics (e.g., epoxy, polyimide, orfluoropolymers). The substrate 12 has open cavities 16 into which IC dieand other discrete electronic components will be placed. The width andlength dimensions of the open cavities 16 are normally slightly largerthan the components that will be inserted to allow tolerance forvariations in the individual component size and room for adding anadhesive compound between the components and the inner periphery of thecavities 16.

Conductive vias 18 through the substrate 12 provide electrical pathwaysbetween the designated front and back surfaces 22F and 22B of thesubstrate 12 upon which electrical interconnects and other circuitelements (inductors, etc.) will be formed. Component lands 20, alsoconductive, may serve as attachment pads for discrete components, andalso as land-grid, ball-grid or pin-grid pads for electricallyconnecting the resultant IC package to a printed circuit board or othersystem-level circuit structure.

With reference to FIG. 2A, a method of assembling the package beginswith the aforementioned substrate 12 being mounted front-side down ontoa die alignment vacuum plate 24. Various IC dice and discrete electricalcomponents (active or passive) to be embedded in the substrate 12 areplaced within the cavities 16. Preferably, IC dice will be place activeside 32 down, so that the active side 32 will be generally coplanar withthe front surface 22F of the substrate. In this way, we don't need touse a substrate having the same thickness as the IC dice, and thevarious IC dice being embedded need not all have the same thickness.Vacuum openings 26 in the vacuum plate 24 will hold the substrate 12,and the IC dice and other discrete components 30 in a fixed position.

With reference to FIG. 2B, normally the components 30 will be somewhatsmaller in length and width dimensions than the cavities 16 in whichthey are place. The gaps between the components 30 and the innerperipheries of the cavities 16 are filled with an adhesive compound 34.After curing of the adhesive compound 34, the substrate 12 with itsembedded components 30 is released by the vacuum plate 24. The curedadhesive compound 34 now holds the embedded components 30 in place.Depending on the adhesive compound being used to fill the gaps, thecuring can be performed by application of heat (e.g., in a furnace) orby ultraviolet light. A self-curing adhesive (e.g., an epoxy resin withcatalyst) could be also be used.

The designated back side of the package (opposite from that containingthe active surfaces on the die) may be kept relatively planar bycontrolling the thicknesses of the die and discrete components, or maybe made planar, if needed, by performing a post-embedding grind process,with a liquid dielectric coating added to facilitate the planarizing.

With reference to FIGS. 2D through 2F, thin-film deposition andphotolithographic etching processes are used to build-up one or morelayers circuit features over both surfaces 22B and 22F of the substrateassembly 12. On each side, there can be either a single layer ofinterconnects and other integrated circuit features, or, more usually,multiple layers of interconnects and features separated by dielectricmaterial layers and connected where needed by vias.

For example, as seen in FIG. 2D, a thin-film metallic layer 38 may bedeposited over the front surface 22F of the substrate assembly 12,followed by a photolithographic mask layer 40. After patterning andetching of the thin-film metallic layer 38, removal of the mask layer40, and possible repeating of the deposition and patterning ofadditional layers, such as a dielectric layer, integrated circuitfeatures result. These circuit features may include metal lands for andinterconnects between the embedded IC dice and other embedded components30, as well as integrated passive elements, such as thin-film inductors.

Likewise, further integrated circuit features are also formed on theback surface 22B, including metallic lands, by means of successivedeposition, patterning and etching using one or more thin-film and masklayers 42 and 44, as seen in FIG. 2E.

The result is a substrate assembly 12 with patterned circuitry 38 and 42on both front and back sides, 22F and 22B, of the substrate. As alreadynoted with reference to FIGS. 1A and 1B, the circuitry on opposite sidesof the substrate assembly 12 in FIG. 2F are connected to each other bymeans of the vias 18 that were pre-formed in the starting substrate.

With reference to FIG. 2G, additional electronic components can beattached to the resulting structure at metal lands on one of thesurfaces, for example, above the front surface 22F. This may include die50 attached with wire bonds 52, leaded packages 54 attached with theirleads 56, ball-grid-array (BGA) packages 58 attached with solder balls60, and discrete components 62. The opposite side of the assembly 12,for example, back side 22F, may have contact pads formed thereon, suchas a BGA structure of solder balls 66. Alternatively, pins could beattached at metal lands on the back surface to form a pin-grid-array(PGA) package structure. Or, the lands themselves, formed on the backsurface's thin film layer 42 in FIGS. 2E and 2F, could define aland-grid-array.

With reference to FIG. 2H, the electronic components 50, 54, 58, etc.above the front surface 22F may optionally be covered by an epoxyover-mold 70, coating or lid cover to protect them from damage duringhandling of the assembled package. Finally, the wafer 10 seen in FIG.1A, now a completed package assembly, undergoes saw singulation intoindividual packages 74, 75, etc., with the cuts made along the dashedlines indicated in FIG. 1A that demarcate the various segments.

1. A method of assembling an multi-component electronic package,comprising: providing a package substrate having defined front and backsurfaces, with conductive vias through the package substrate providingelectrical connections between the front and back surfaces, and withmultiple openings in the package substrate adapted to receive electroniccomponents; securing the package substrate on a vacuum support; placingmultiple electronic components within the multiple openings of thepackage substrate, the electronic components being secured in place bythe vacuum support, each electronic component being spaced from an innerperiphery of its corresponding opening of the package substrate by agap; depositing an adhesive filler material within the gap and thencuring the adhesive filler material, such that the electronic componentswithin the openings are permanently secured to the package substrate;and forming circuit features in one or more layers on both front andback surfaces of the package substrate, circuit features on oppositesurfaces of the package substrate being electrically connected to eachother by means of the conductive vias through the package substrate, thecircuit features including conductive interconnects that areelectrically connected to the multiple electronic components, thecircuit features on at least one surface of the package substrateincluding a set of contact pads defining external connection locationsfor the assembled multi-component electronic package.
 2. The method asin claim 1, wherein the package substrate comprises a dielectricmaterial with metallic vias therethrough.
 3. The method as in claim 1,wherein at least one of the multiple electronic components placed withinthe openings of the package substrate is an integrated circuit (IC) die.4. The method as in claim 3, wherein the IC die has an active surfaceand the IC die is placed in an opening of the package substrate with itsactive surface coinciding with designated front surface of the packagesubstrate.
 5. The method as in claim 1, wherein the circuit features areformed by photolithography, with deposition a thin-film feature layerand a mask layer over the feature layer, patterning and etching of thefeature layer using the mask layer, removal of the mask layer, andrepeating to pattern additional feature layers.
 6. The method as inclaim 1, wherein the circuit features include integrated passive circuitelements.
 7. The method as in claim 1, wherein the circuit features aresuccessive formed first on one surface of the package substrate and thenon the other surface of the package substrate.
 8. The method as in claim1, wherein the circuit features formed on the package substrate includeconductive lands and the method further comprises attaching additionalelectronic components onto the designated front surface of the packagesubstrate with electrical connections to the conductive lands.
 9. Themethod as in claim 8, further comprising providing a protective coveringover the additional electronic components.
 10. The method as in claim 1,wherein the set of contact pads are formed as circuit features on adesignated back surface of the package substrate.
 11. The method as inclaim 10, wherein the set of contact pads form a package contactstructure selected from the group consisting of a land-grid-array,ball-grid-array and pin-grid-array.
 12. The method as in claim 1,wherein the package substrate is a wafer for assembling multiplepackages, and the method, after forming the circuit features, furtherincludes segmenting the wafer into individual assembled packages.
 13. Amulti-component electronic package, comprising: a package substratehaving designated front and back surfaces with conductive vias throughthe substrate; multiple electronic components embedded within thepackage substrate and secured thereto by a cured adhesive material; andone or more layers of circuit features on both front and back surfacesof the package substrate, circuit features on opposite surfaces of thepackage substrate being electrically connected to each other by means ofthe conductive vias through the package substrate, the circuit featuresincluding conductive interconnects that are electrically connected tothe multiple electronic components, the circuit features on at least onesurface of the package substrate including a set of contact padsdefining external connection locations for the electronicmulti-component package.
 14. The package as in claim 13, wherein thepackage substrate comprises a dielectric material with metallic viastherethrough.
 15. The package as in claim 13, wherein at least one ofthe multiple electronic components embedded within the package substrateis an integrated circuit (IC) die.
 16. The package as in claim 13,wherein the circuit features include integrated passive circuitelements.
 17. The package as in claim 13, wherein the circuit featuresformed on the package substrate include conductive lands and the packagefurther comprises additional electronic components attached to thedesignated front surface of the package substrate with electricalconnections to the conductive lands.
 18. The package as in claim 17,further comprising a protective covering over the additional electroniccomponents.
 19. The package as in claim 13, wherein the set of contactpads form a package contact structure selected from the group consistingof a land-grid-array, ball-grid-array and pin-grid-array.